Atari 8bit, Cartridge Port Pin Assignments

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A	B	C	D	E	F	H	J	K	L	M	N	P	R	S

1	2	3	4	5	6	7	8	9	10	11	12	13	14	15

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Pin Function

1 ~S4 R/~W late: Chip Select for area $8000 to $9FFF
2 A3: CPU Address Bus Line A3
3 A2: CPU Address Bus Line A2
4 A1: CPU Address Bus Line A1
5 A0: CPU Address Bus Line A0
6 D4: CPU Address Bus Line A3
7 D5: CPU Data Bus Line D5
8 D2: CPU Data Bus Line D2
9 D1: CPU Data Bus Line D1
10 D0: CPU Data Bus Line D0
11 D6: CPU Data Bus Line D6
12 ~S5 ~S4: Chip Select for area $A000 to $BFFF
13 +5V: Power Supply
14 RD5 RD4: Disable RAM $A000 to $BFFF
15 ~CCTL: Any read or write to the cartridge control area ($D500) area brings this line low.

A RD4 B02: Chip Select for area $8000 to $9FFF
B Gnd: Power Supply return
C A4: CPU Address Bus Line A4
D A5: CPU Address Bus Line A5
E A6: CPU Address Bus Line A6
F A7: CPU Address Bus Line A7
H A8: CPU Address Bus Line A8
J A9: CPU Address Bus Line A9
K A12: CPU Address Bus Line A12
L D3: CPU Data Bus Line D3
M D7: CPU Data Bus Line D7
N A11: CPU Address Bus Line A11
P A10: CPU Address Bus Line A10
R R/~W: CPU Control Bus R/!W Line
S B02: 6502 Phase 2 clock (Use to I/F to support chips)

NB: Descriptions only given for left cartridge allocation, as right cartidge only found on 800 model

Key
	Left Slot Only
	Right Slot Only (800)
	Either/Both Slots

Pin Usage

!CCTL

Use for things like the !CS pin of any chips you add to the cartridge port. For example, you can add a 6520 to a cartridge port and by tying this line to the !CS, the 6520 will be mapped into the $D500 hardware region.

!S4

Chip Select (!CS) line for the 8Kb memory area $8000-$9FFF (Left Cartridge). Active low on read or write access. only active if RD4 is held low.

!S5

Chip Select (!CS) line for the 8Kb memory area $A000-$BFFF (Left Cartridge). Active low on read or write access.

R4

Disables RAM in the high cart $8000-$9FFF (Right Cartridge) region so that user defined hardware can be accessed. Tie high (to +5 Volts) to enable. !S4 Line will become active when tied in aactive state.

R5

Disables RAM in the high cart $A000-$BFFF (Left Cartridge) region so that user defined hardware can be accessed. Tie high (to +5 Volts) to enable. !S5 Line will become active when tied in aactive state.

B02

CPU Phase 2 clock signal. Used with most 65xx support chips. Seems to have been called something like 'B' or 'VMA' on the 68xx series.

Standard 8Kb (2 Chip) card Schimatic

Standard 8Kb (1 Chip) card Schimatic

Possible Atari type 16Kb (1 Chip) card Schimatic

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Last Update: 31 Dec 1999

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